IEEE Global Education for Microelectronics Systems "I-GEMS"
Steering Committee for the IGEMS Initiative
Dr. Andrzej Rucinski (Chair), University of New Hampshire, a.rucinski@ieee.org
Dr. James Aylor, University of Virginia, j.aylor@ieee.org
Dr. Don Bouldin, University of Tennessee, d.bouldin@ieee.org
Dr. Juan-Antonio Carballo, (DATC Chair), Argon Venture Partners, jantonio@ieee.org
Dr. Ted Kochanski, University of New Hampshire, tedpk@ieee.org
The IEEE Global Education for Microelectronics Systems (I-GEMS) initiative has been launched under the auspices of DATC (Design Automation Technical Committee of the IEEE Computer Society) to promote and facilitate the global design of microelectronic systems.
The initial project for I-GEMS is to establish a web-based, globally-accessible repository of high quality, reusable testbenches for trusted virtual components or intellectual property (IP). The repository is intended to facilitate the development of sophisticated high-reliability integrated circuits for mission-critical applications by a team of designers who may be geographically dispersed.
To utilize the repository, a supplier uploads both a testbench and a corresponding virtual component to the IEEE secure website and supplies information about the testbench, component (language), simulation (tool, version, library) and authors/owners. The simulation is then repeated on the IEEE webserver and the results reported initially just to the user. A charge is assessed for this self-test. Once the responses on the IEEE webserver match those in the testbench, the user may elect to receive a certificate and publish the results.
If the public option is selected, the testbench is placed in an open respository as well as a description of the component. A certificate is produced for the user with a checksum for the testbench-component tested. A charge is assessed for this certification. The user may then retain the component for proprietary reasons or contribute it to the IEEE website for others to use at no charge. The repository is modeled on MOSIS, with the website self-sustainable via user fees and with substantial discounts for educational users to encourage university innovation.
Background
While microelectronics has revolutionized the world in the past forty years, the availability of extremely complex, globally-sharable, and reusable microelectronic building blocks and virtual components(collectively frequently referred to as "IP Cores"), will usher in the next revolution in science and engineering research, education, and innovation. Today, there are customer-centric corporate sites (e.g. MathWorks sponsored for MatLab and Simulink models, Xilinx sponsored for IP Cores for Xilinx FPGAs). There are also websites such as TechOnline that allow certain tools and equipment to be taken for a "virtual test-drive, " and intellectual property-exchange consortia such as that recently announced by IBM. However, there is no one site that addresses the challenge and opportunity posed by globally collaborative design of microelectronic-based systems. We propose to develop the prototype Microelectronic Design Engineering Virtual Organization (I-GEMS WEB) I-GEMS Web with the cyberinfrastructure for the global design of microelectronic systems based on a repository of reusable IP blocks and course materials that are peer-reviewed for quality.
I-GEMS Web is a web-based self-sustaining Engineering Virtual Organization ("EVO") that is operated as a not-for-profit MOSIS-like entity by the IEEE (formally known as the Institute of Electrical and Electronic Engineers) to take advantage of the IEEE's global extent and reputation for globally adopted standards (e.g. 8.02.11, etc). The initial goal of the I-GEMS WEB is to effect a web-based means of submitting IP Core-based designs and supporting verified testing and performance characterization tools and data sets (frequently referred to as "Testbenches"); that is equivalent to publication in internationally accepted peer-reviewed journals (e.g. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems) often referred to as "Philadelphia List" publications.
When fully implemented, the I-GEMS WEB, governed by the IEEE Global Microelectronics Education Innovation Initiative Steering Committee (referred to as "I3 Steering Committee" to be elaborated upon later), will provide the microelectronics-focused technology development, education and systems engineering community with a global virtual society. Thus I-GEMS WEB is a prototype of a 2nd Generation EVO that goes beyond an operational VO community by enabling design, test, and implementation of complex microelectronics-based-systems from both the practice and education perspectives.
I-GEMS WEB will feature web-based access to: advanced and expensive Instrumentation; sophisticated development and testing software Tools; a Repository for peer-reviewed and tested Trusted IP Cores; and associated Models; a Repository for verified Testbenches; and peer reviewed supporting Tutorials; and informal "Blog-like" on-line shared Information Exchanges. In addition to its cyber-elements, the I-GEMS WEB will take advantage of the existing IEEE educational and information sharing channels (e.g. IEEE Boston Section Short Courses and Lecture Series) and other microelectronic community mechanisms (e.g. Design Automation Conference (DAC) International Conference on Computer Aided Design (ICCAD), European Workshop on Microelectronics Education (EWME), Microelectronics Systems Education Conference (MSE), IEEE East-West Design & Test Symposium (EWDTS) Conferences and if necessary work to create new mechanism for the dissemination of knowledge through formal and informal Courses, Workshops, Tutorials and Conferences.
Increasingly, generic virtual components are produced by highly skilled and cost-effective designers in countries like India, China, Estonia, and Armenia. However, these components must be of proven quality and must be integrated into a cohesive system of hardware and software that satisfies the customer's system requirements and facilitates testing of the final product. Effective communication between the customer and the system designer is essential for a timely implementation.
We propose to develop a repository of high quality, reusable virtual components (e.g. IP Cores) Testbenches and associated course materials. These will be peer-reviewed for quality with the goal of this effort being considered an equivalent to a traditional IEEE Philadelphia List publication. A major side benefit of this on-line peer-reviewed repository will be that designers and modelers will now have the equivalent of the academic's peer-reviewed publications citations to demonstrate their prowess; much like a graphic designer's portfolio or a musician's recital recording. This globally accessible recognition of the engineers work should help stimulate the innovation and creativity required to continue to advance the state-of-the-art and may make the field more attractive to disabled, minority, retired and other non-traditional participants.
Integration of Research and Education
Research anticipated for the development of a viable inventory of global micro-electronics IP core components
After receipt and inventory validation of the IP core components, several additional design aspects need to be assessed and improved in order to result in a viable versatile library of trusted design elements for globally develop-able micro-electronics .
• Trusted Components, need for ascertaining the trustworthiness and safety of the received IP core components by review and certification of the absence of "malware" in the submitted IP core components
• Computed Components, need for developing multiple (equivalent in result) instances of the particular received IP core components along performance (e.g., throughput, latency) versus cost (e.g., real-estate in logic slices) tradeoff curves
• Reliability Wrappers for Computed Components, need for providing support for fault-tolerant redundant use, when required, of the generated IP core components
Trusted Components
The continual improvements in both the performance capacity of ASIC/FPGA hardware and the internal memory capacity of these devices has led to new opportunities for very complex IP core components to be developed. This, in turn, has increased the need for techniques to support the "trustable" development of these performance sensitive applications. Key research questions of interest include , but are not limited to:
Students need to follow a well-founded methodology in which system requirements are developed first and then converted into executable specifications prior to model development. This procedure will result in high quality models that can be integrated with others developed by other team members who may be located anywhere in the world. This activity gives students the same experience that commercial designers follow in developing new products. It will also establish in the minds of students that their models must achieve a minimum quality level that can later be optimized for different performance metrics such as size, delay and power consumption.